The present invention relates to electronic postage meters, and more specifically to a data protection system for electronic postage meters having multiple non-volatile memories (NVMs).
Various electronic postage meter systems have been developed, as for example the systems disclosed in U.S. Pat. No. 3,978,457 for Microcomputerized Electronic Postage Meter Systems, U.S. Pat. No. 3,938,095 for Computer Responsive Postage Meter, European patent application No. 80400603.9, filed May 5, 1980 for Electronic Postage Meter Having Improved Security and Fault Tolerance Features, U.S. Pat. No. 4,301,507, for Electronic Postage Meter Having Plural Computing Systems, and copending application Ser. No. 447,815, filed Dec. 8, 1982, for Stand-Alone Electronic Mailing Machine.
Generally, electronic postage meters include some form of non-volatile memory capability to store critical postage accounting information. This information includes, for example, the amount of postage remaining in the meter for subsequent printing and the total amount of postage already printed by the meter. Other types of accounting or operating data may also be stored in the non-volatile memory, as desired.
However, conditions can occur in electronic postage meters where information stored in non-volatile memory may be lost. A total line power failure or fluctuation in voltage conditions can cause the microprocessor associated with the meter to operate erratically and either cause erasure of data or the writing of spurious data in the non-volatile memory. The erasure of data or the writing of spurious data in the non-volatile memory may result in a loss of critical accounting information. Since the accounting data changes with the printing of postage and is not permanently stored elsewhere, there is no way to recapture or reconstruct the lost information. Under such circumstances, it is possible that a user may suffer a loss of postage funds.
To minimize the likelihood of a loss of information stored in the non-volatile memory, various approaches have been adopted to insure the high reliability of electronic postage meters. It is known from aforementioned U.S. Pat. No. 3,978,457 and aforementioned copending application Ser. No. 447,815 to provide a microprocessor controlled electronic postage meter having memory architecture which includes a temporary storage memory for storing accounting data reflecting each meter transaction and a non-volatile memory to which the accounting data is transferred during the power down cycle of the meter. With such a memory architecture it is known to provide a memory protection circuit for transferring data from the temporary memory to the NVM during the power down cycle, see U.S. Pat. No. 4,445,198, entitled, Memory Protection Circuit For An Electronic Postage Meter.
Another approach for preserving the stored accounting data has been the use of redundant non-volatile memories. One such redundant memory system is disclosed in patent application Ser. No. 343,877, filed Jan. 29, 1982, in the name of Frank T. Check, Jr., and entitled Electronic Postage Meter Having Redundant Memory. With such redundant memory system the two redundant non-volatile memories are interconnected with a microprocessor by way of completely separate data and address lines to eliminate error conditions. The data may be applied to the memories simultaneously or sequentially at different times. Such a system minimizes the possibility of non-detectable and/or non-correctable errors resulting from transients.
Another redundant memory system is disclosed in the aforementioned European patent application No. 80400603.9. In such patent application, accounting data is written into each of the two non-volatile memories, designated BAMs, twice during each postage meter transaction, once in temporary form and once in permanent form to minimize the loss of accounting data during microcomputer failure. During a power failure a microprocessor sets a pair of redundant flip-flops to provide a first signal, after a predetermined time period to allow completion of any ongoing BAM register updates, which signal inhibits further writing in the BAMs and a second signal, after another predetermined time period, which signal inhibits further operation of the microprocessor. These signals are generated in a particular time sequence in an effort to prevent spurious operation during the power down cycle.
Another system which includes multiple non-volatile memories is disclosed in copending patent application Ser. No. 643,219, filed on even date herewith, entitled Non-Volatile Memory System With Real Time And Power Down Data Storage Capability For An Electronic Postage Meter. In this system a first NVM stores accounting data of each postage transaction in real time during each trip cycle, while a second NVM has postage transaction accounting data transferred from a volatile memory and written into the second NVM only during a power down cycle of the meter. However, with such a non-volatile memory system it is advantageous to inhibit further writing in the first or real time NVM once a power down cycle begins.